In a capacitively coupled plasma reactor, control over dissociation has been achieved with a wide impedance match space at very high RF source power over a very wide chamber pressure range. Such a wide operating range is attributable, at least in part, to a unique feature of the overhead electrode matched to the RF power source by a fixed impedance matching stub with the following features. First, the electrode capacitance is matched to the plasma reactance at a plasma-electrode resonant frequency. The stub resonant frequency, the plasma-electrode resonant frequency and the source frequency are nearly matched at a VHF frequency. A highly uniform etch rate across the wafer is attained through a number of features. These features include, among other things, the adjustment of the bias power feedpoint impedance on the electrostatic chuck to provide a radially uniform RF impedance across the chuck for both its role as an RF bias power applicator and as an RF return for the VHF source power from the overhead electrode. This adjustment is made by dielectric sleeves around the bias feed line of uniquely selected dielectric constants and lengths. Another feature is a dielectric ring process kit for the cathode periphery to combat edge effects. Other features that can further improve process or etch rate distribution uniformity include dual zone gas feeding, curving of the overhead electrode and plasma steering magnetic fields. A plasma reactor that includes many of these key features provides an etch rate distribution uniformity that surpasses the conventional art.
With rapid shrinking of circuit feature sizes, the requirements for etch rate distribution uniformity are so stringent that small temperature variations across the wafer must now be minimized or eliminated, with the added proviso that future sophisticated process recipes designed to meet the latest stringent requirements will require agile and highly accurate time-changing wafer temperature profiling, and/or RF heat load profiling. Such changes must be effected or compensated with the greatest temperature uniformity across the wafer. How to do all this without degrading the now highly uniform, etch rate distribution currently afforded by the reactor is a difficult problem. Moreover, such highly accurate and agile temperature control or profiling requires accurate temperature sensing at the wafer. However, introduction of temperature probes near the wafer will create parasitic RF fields which distort the fine effects of the feed-point impedance dielectric sleeves and the dielectric ring process kit, defeating their purpose. Temperature non-uniformities at the wafer arising from lack of control, to the extent that they impact the etch chemistry, will have the same ultimate effect of distorting an otherwise uniform environment.
Conventional cooling systems for regulating the temperature of the wafer support pedestal or electrostatic chuck employ a refrigeration system that cools a refrigerant or coolant medium using a conventional thermal cycle and transfers heat between the coolant and the electrostatic chuck through a separate liquid heat transfer medium. The coolant may be a mixture of deionized water with other substances such as glycol and (or) perfluoropolyethers. One problem with such systems is that, at high RF power levels (high RF bias power or high RF source power or both), such cooling systems allow the wafer temperature to drift (increase) for a significant period before stabilizing after the onset of RF power. Such temperature drift has two phases. In a brief initial phase, the electrostatic chuck is at an ambient (cold) temperature when RF power is first applied, so that the temperature of the first wafer to be introduced climbs rapidly toward equilibrium as the RF heat load slowly heats the chuck. This is undesirable because the wafer temperature rises uncontrollably during processing. Even after the electrostatic chuck (ESC) has been heated by the RF heat load, the wafer temperature drifts upwardly and slowly approaches an equilibrium temperature. Such drift represents a lack of control over wafer temperature, and degrades the process. The drift is caused by the inefficiency of the conventional cooling process.
Another problem is that rapid temperature variations between two temperature levels cannot be carried out for two reasons. First, the heat transfer fluid that provides thermal transfer between the ESC and the coolant has a heat propagation time that introduces a significant delay between the time a temperature change is initiated in the refrigeration loop and the time that the wafer actually experiences the temperature change. Secondly, there is a heat propagation time delay between the cooled portion of the ESC base and the wafer at the top of the ESC, this time delay being determined by the mass and heat capacity of the materials in the ESC.
One of the most difficult problems is that under high RF heat load on the wafer requiring high rates of thermal transfer through the cooled ESC, the thermal transfer fluid temperature changes significantly as it flows through the fluid passages within the ESC, so that temperature distribution across the ESC (and therefore across the wafer) becomes non-uniform. Such non-uniformities have not presented a significant problem under older design rules (larger semiconductor circuit feature sizes) because etch rate uniformity across the wafer diameter was not as critical at the earlier (larger) feature sizes/design rules. However, the current feature sizes have dictated the extremely uniform electric fields across the ESC achieved by the features described above (e.g., RF bias feedpoint impedance adjustment, process kit dielectric edge rings). However, the high RF heat loads, dictated by some of the latest plasma etch process recipes, cause temperature non-uniformities across the wafer diameter (due to sensible heating of the thermal transfer fluid within the ESC) that distort an otherwise uniform etch rate distribution across the wafer. It has seemed that this problem cannot be avoided without limiting the RF power applied to the wafer. However, as etch rate uniformity requirements become more stringent in the future, further reduction in RF power limits to satisfy such requirements will produce more anemic process results, which will ultimately be unacceptable. Therefore, there is a need for a way of extracting heat from the wafer under high RF heat load conditions without introducing temperature non-uniformities across the ESC or across the wafer.